In this session we will see the concepts about case,casex and casez.
In General case,casex and casez will do the bit-wise comparisons between the selecting the case expression and individual case statements. Comparisons are performed by using the identity operator === instead of equality ==. casex ignores any bit position containing X or Z. casez ignores bit positions with Z. In verilog ? and Z characters to represent the Z state.
CASE:
case statement considers x or z as it is. If a case expression containing x or z will only match a case item containing x or z at the corresponding bit positions. If no case item matches the default item is executed.
module case_example();
reg [3:0] data;
always @ (data)
case(data)
4'b1zzx : begin
$display($time," 4'b1zzx is selected, DATA %b",data);
end
4'b01?? : begin
$display($time," 4'b01?? is selected, DATA %b",data);
end
4'b001? : begin
$display($time," 4'b001? is selected, DATA %b",data);
end
default : begin
$display($time," default is selected, DATA %b",data);
end
endcase
initial begin
data = 0;
#2 data = 4'b101x;
#2 data = 4'b1x1x;
#2 data = 4'b1001;
#2 data = 4'b0010;
#2 data = 4'b01x1;
#2 data = 4'b0000;
#2 data = 4'b001z;
#2 data = 4'b001x;
#2 $finish;
end
endmodule
OUTPUT
0 default is selected, DATA 0000
2 default is selected, DATA 101x
4 default is selected, DATA 1x1x
6 default is selected, DATA 1001
8 default is selected, DATA 0010
10 default is selected, DATA 01x1
12 default is selected, DATA 0000
14 4'b001? is selected, DATA 001z
16 default is selected, DATA 001x
$finish called from file "testbench.sv", line 31.
$finish at simulation time 18
V C S S i m u l a t i o n R e p o r t
2 default is selected, DATA 101x
4 default is selected, DATA 1x1x
6 default is selected, DATA 1001
8 default is selected, DATA 0010
10 default is selected, DATA 01x1
12 default is selected, DATA 0000
14 4'b001? is selected, DATA 001z
16 default is selected, DATA 001x
$finish called from file "testbench.sv", line 31.
$finish at simulation time 18
V C S S i m u l a t i o n R e p o r t
Example 2:
module case_example();
reg [3:0] data;
always @ (data)
case(data)
4'b10xz : begin
$display($time," 4'b10xz is selected, DATA %b",data);
end
4'b01xx : begin
$display($time," 4'b01xx is selected, DATA %b",data);
end
4'b001? : begin
$display($time," 4'b001? is selected, DATA %b",data);
end
default : begin
$display($time," default is selected, DATA %b",data);
end
endcase
initial begin
data = 0;
#2 data = 4'b10xz;
#2 data = 4'b01xx;
#2 data = 4'b1001;
#2 data = 4'b0010;
#2 data = 4'b01x1;
#2 data = 4'b0000;
#2 data = 4'b001z;
#2 data = 4'b001x;
#2 $finish;
end
endmodule
OUTPUT:
0 default is selected, DATA 0000
2 4'b10xz is selected, DATA 10xz
4 4'b01xx is selected, DATA 01xx
6 default is selected, DATA 1001
8 default is selected, DATA 0010
10 default is selected, DATA 01x1
12 default is selected, DATA 0000
14 4'b001? is selected, DATA 001z
16 default is selected, DATA 001x
$finish called from file "testbench.sv", line 31.
$finish at simulation time 18
V C S S i m u l a t i o n R e p o r t
2 4'b10xz is selected, DATA 10xz
4 4'b01xx is selected, DATA 01xx
6 default is selected, DATA 1001
8 default is selected, DATA 0010
10 default is selected, DATA 01x1
12 default is selected, DATA 0000
14 4'b001? is selected, DATA 001z
16 default is selected, DATA 001x
$finish called from file "testbench.sv", line 31.
$finish at simulation time 18
V C S S i m u l a t i o n R e p o r t
casex statement considers both x and z as don't care. If a case expression containing x or z will only match a case item containing 0 or 1 at the corresponding bit positions.
//casex ignores comparison any bit containing an "X or "Z"
//verilog use ? and Z characters to represent "Z" state
module casex_example();
reg [3:0] data;
always @ (data)
casex(data)
4'b1zzx : begin // bit 2:0 is don't care bits
$display($time," 4'b1zzx is selected, DATA %b",data);
end
4'b01?? : begin // bit 1:0 is don't care bits
$display($time," 4'b01?? is selected, DATA %b",data);
end
4'b001? : begin // bit 0 is don't care bit
$display($time," 4'b001? is selected, DATA %b",data);
end
default : begin
$display($time," default is selected, DATA %b",data);
end
endcase
initial begin
data = 0;
#2 data = 4'b101x;
#2 data = 4'b1x1x;
#2 data = 4'b1001;
#2 data = 4'b0010;
#2 data = 4'b01x1;
#2 data = 4'b0000;
#2 data = 4'b001z;
#2 data = 4'b001x;
#2 $finish;
end
endmodule
OUTPUT:
0 default is selected, DATA 0000
2 4'b1zzx is selected, DATA 101x4 4'b1zzx is selected, DATA 1x1x
6 4'b1zzx is selected, DATA 1001
8 4'b001? is selected, DATA 0010
10 4'b01?? is selected, DATA 01x1
12 default is selected, DATA 0000
14 4'b001? is selected, DATA 001z
16 4'b001? is selected, DATA 001x
$finish called from file "testbench.sv", line 31.
$finish at simulation time 18
V C S S i m u l a t i o n R e p o r t
CASEZ
casez statement considers z bit position as don’t care. If a case expression containing z will only match a case item containing 0 or 1 or x at the corresponding bit positions.
//casez ignores comparison any bit containing an "Z"
//verilog use ? and Z characters to represent "Z" state
module casez_example();
reg [3:0] data;
always @ (data)
casez(data)
4'b1zzx : begin // Don't care 1:0 bits bit 0 should match with x
$display($time," 4'b1zzx is selected, DATA %b",data);
end
4'b01?? : begin // bit 1:0 is don't care bits
$display($time," 4'b01?? is selected, DATA %b",data);
end
4'b001? : begin // bit 0 is don't care bit
$display($time," 4'b001? is selected, DATA %b",data);
end
default : begin
$display($time," default is selected, DATA %b",data);
end
endcase
initial begin
data = 0;
#2 data = 4'b101x;
#2 data = 4'b1x1x;
#2 data = 4'b1001;
#2 data = 4'b0010;
#2 data = 4'b01x1;
#2 data = 4'b0000;
#2 data = 4'b001z;
#2 data = 4'b001x;
#2 $finish;
end
endmodule
OUTPUT:
0 default is selected, DATA 0000
2 4'b1zzx is selected, DATA 101x4 4'b1zzx is selected, DATA 1x1x
6 default is selected, DATA 1001
8 4'b001? is selected, DATA 0010
10 4'b01?? is selected, DATA 01x1
12 default is selected, DATA 0000
14 4'b001? is selected, DATA 001z
16 4'b001? is selected, DATA 001x
$finish called from file "testbench.sv", line 31.
$finish at simulation time 18
V C S S i m u l a t i o n R e p o r t
Hope this logic's will be useful to everyone !!!
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Great analysis! Below is something that I have experimented using CASEZ. Just thought this might add your analysis.
ReplyDeletemodule din;
logic [2:0]i;
initial begin
i = 3'b100; cas(i);
i = 3'b101; cas(i);
i = 3'b10z; cas(i);
i = 3'b10x; cas(i);
end
task cas(logic[2:0]a);
casez(a) //CASEZ
3'b100 : $display("100");
3'b101 : $display("101");
3'b10z : $display("Z -> 100 or 101");
3'b10x : $display("X -> 100 or 101");
default : $display("OTHERS");
endcase
endtask
endmodule
OUTPUT:
100
101
100
Z -> 100 or 101
Thanks for the feedback!!! Nice Example.
DeleteKeep supporting !!!
Nice explanation
ReplyDeleteClear explanations thanks
ReplyDelete