Blocking and Non Blocking in Verilog

Hi Everyone !!!,

In this session we are going to the concepts and tricky codes about Blocking and Non Blocking in Verilog, 

Blocking Statement:

    Blocking statement executed sequentially. It blocks the next statement execution until the current statement completion.

    Blocking statement is a one step process. Which means Evaluate the RHS of the expression and update the LHS in same time step.

    Blocking statements are executed in active region.Blocking statement always suffer from Race condition since two process (Evaluation&assignment)  happens in same time step.

      Blocking statements can be used in always,initial and assign statements.

    Syntax:

          value= <timing control><expression?

       

         Here value is data type that is valid for procedural assignment statement

                =  is the assignment operator

         timing control- can either be delay control (#6) or en event control (eg: @posedge clk)

      eg: data=0; 

            a= #4 1;

Non Blocking Statement:  

        Non Blocking statement executed parallel. It allows you to schedule a assignment without blocking the procedural flow. It doesn't block the next statement until the current statement completion.

          Non Blocking statement occurred in active region and LHS assignment will happen in Non Blocking Assignment (NBA) region.  

        Non Blocking is a two step process:

                * Evaluate the RHS expression at the beginning of time step .

                * LHS assignment will be happened at the end of time step.

         Non Blocking statements can be used in always,initial. It can't be used in assign statement.

           

 Syntax:

          value<= <timing control><expression?

       

         Here value is data type that is valid for procedural assignment statement

                <=  is the assignment operator

         timing control- can either be delay control (#6) or en event control (eg: @posedge clk)

      eg: data<=0; 

            a<= #4 1;

Note:

       For combinational logic blocking and sequential logic non blocking assignments are preferred.

       

TRICKY PROGRAMS!!!!!!!

1)            module example1;

                    reg a=0,b=1;

                    initial begin

                       a<=b;

                       b<=a;

                        $monitor("a=%0d,b=%0d",a,b)

                     end

                endmodule

output:

    a=1,b=0

                     

Working logic:

            Evaluation of RHS will happens in first time step(active region)

            Assignment happens in at the end of time step(non blocking region). So values gets swapped.

            For swapping two variable without using third variable non blocking assignment will be used.

2)          module example2;

                  reg a,b,c,d,e,f;

                  //**Blocking Assignments

                  initial begin

                      a= #10 1;  //Here simulator assigns 1 for a at time of 10

                      b= # 2 0;  // B gets assigned at simulation time of 12

                      c= #4   1; // C gets assigned at simulation time of 16

                   end

                 //** Non Blocking Assignments

                   initial begin

                       d<= #10; //Here simulator assigns 1 for a at time of 10

                       e<=#2 0; // e gets assigned at simulation time of 2

                       f<=#4 1; // f gets assigned at simulation time of 4

                    end

                   initial begin

                        $monitor($time,"a=%b b=%b c=%b d=%b e=%b f=%b",a,b,c,d,e,f);

                   end

                 endmodule

3)     When you schedule multiple non-blocking assignments to occur in same variable in a particular time slot, the simulator cannot guarantee the order in which it processes the assignments. the final value of the variable is indeterminate.

                 module example3;

                    reg a=1;

                    initial begin

                       a<=#4 0;

                       a<=#4 1;

                        $monitor("a=%0d,b=%0d",a,b)

                     end

                endmodule

output:

    Here "a" value is indeterminate.

4)       If the simulator executes two procedural bloks concurrently and the procedural block contains non blocking assignment operators with same time delay so the final value is indeterminate.

                module example4;

                    reg a;

                    initial  a<=#4 0;

                    initial  a<=#4 1;

                    initial begin

                        $monitor("a=%0d,b=%0d",a,b)

                     end

                endmodule

output:

    Here "a" value is indeterminate.

5)        When multiple Non Blocking assignments with timing controls are made to same variable. the assignments can be made without cancelling previous non blocking assignments.

               module example5;

                    reg a=0;

                    reg[2:0] i;

                    initial begin

                        for(i=0;i<=5;i++) begin

                            a<=#(i*10)i[0];

                        end

                    end

                endmodule

Output:

        @time 0   a=0;

        @time 10 a=1;

        @time 20 a=0;

        @time 30 a=1;

        @time 40 a=0;

        @time 50 a=1;

Hope this logics will be useful to everyone !!!

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