How to Randomize a Non Random Variable in System Verilog

Hi Everyone!!!!

Today we are going to see the concepts of "How to randomize a Non random Variable "

 System verilog supports multiple methods to generate random data. By using any of these we can randomize a variable.

System Verilog randomization methods

• $urandom() and $random
• $urandom_range()
• std::randomize()
• randomize()                                                                                                                      

By Using $urandom() and random()       

•         This function returns a new 32 bit random number.
•          $random generates signed number.
•          $urandom generates unsigned number.      

By using $urandom_range()

•           The $urandom_range() function returns an unsigned integer within a specified range. 
•           The function shall return an unsigned integer in the range of maxval ... minval.

    Example 1:

    val = $urandom_range(7,0);

    If minval is omitted, the function shall return a value in the range of maxval ... 0.

    Here it will produce  (7..0)

    Example 2:

    val = $urandom_range(7);

    If maxval is less than minval, the arguments are automatically reversed so that the first argument

    is larger than the second argument.

    Example 3:

    val = $urandom_range(0,7);

    All of the three previous examples produce a value in the range of 0 to 7, inclusive.

By Using std::randomize()

     Variables can be randomized by using std::randomize. It can allowed the inline constraint using "with" clause.

       We can also use as below,

•           std::randomize(variable)
•           std::randomize(variable) with {constraints;};

By Using randomize() 

    The randomize() method can be used to temporarily control the set of random and state variables within a class instance or object. 

     When the randomize() method is called with no arguments, it randomize only rand/randc variables.

     When randomize() is called with arguments, those arguments only will be randomized irrespective of rand/randc declaration.

Example:

    class non_random;

        rand byte x, y;   //random variables

        byte v, w;           //state variables

    endclass

    module TB;

        initial begin

            non_random a = new();

            a.randomize();         // Here random variables(x,y) only will be randomized and v,w won't randomize since it is a state variable

           a.randomize( x );     // Here X alone will be randomized others will be treated as state variable even we declare a variable as rand/randc

           a.randomize( v, w ); // Here v,w are randomized and other variable will be treated as state variable

           a.randomize( w, x ); // Here w,x are randomized 

        end

   endmodule

This mechanism controls the set of active random variables which is conceptually equivalent to making a set of calls to the rand_mode() method to disable or enable.

TRICKY EXAMPLES

 1)        module example;

             bit[31:0] data1;

             bit[63:0] data2;

             bit[31:0] data3;

             bit[31:0] data4;

             bit[31:0] data5;

             bit[31:0] data6;

             bit[31:0] number;

             initial begin

             repeat(10) begin

                       data1=$urandom();  //It will produce 32 bit unsigned number

                       data2={$urandom(),$urandom()};    // It will produce 64 bit unsigned number

                       data3=$random; //It will produce 32 bit signed number

                       data3=$unsigned($random); //It will produce a 32 bit unsigned number

                       data4=$urandom_range(50,30); //It will produce 50 to 30 ranges of values

                       data5=$urandom_range(30); // It will produce 0 to 30 values only

                       data6=$urandom%10 //It will produce 0 to 9 number only

                       number = $urandom & 15; // 4-bit  unsigned random number will be produced. Generally $urandom produce 32 bit number and doing "AND" operation of 15 we will generate random 4 bit number. This is one Trick.

            end

            end

           endmodule

        

 2) 

        module example2;

            bit[7:0] data;

            initial begin

            repeat(4) begin

               std::randomize(data)with{data<4}; //It randomize and produce value less than 4 values only

            end

            end

         endmodule

Note:

The seed is an optional argument that determines the sequence of random numbers generated. The seed can be any integral expression. $urandom(int seed), $random( int seed). For particular seed the same value will be generated whenever we trigger the simulation.

Hope this logic's will be useful to everyone !!!

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