In this article we are going to see the race conditions in verilog,
Race Condition:
When two or more expressions are executed at the same time step, and if the order of the execution is nondeterministic, then the race condition occurs.
Method 1:
module race;
wire p;
reg q;
assign p=q;
initial begin
q=1;
#1 q=0;
#display(p);
end
endmodule
Because the execution of expression evaluation and net update events may be intermingled, race conditions are possible.
Whenever "
The simulator is correct in displaying either a 1 or a 0. The assignment of 0 to q enables an update event for p. The simulator may either continue and execute the $display task or execute the update for p, followed by the $display task.
Method 2:
module race2;
bit clk;
reg[3:0] a;
always #5 clk=~clk;
always @( posedge clk)
a=1;
always @ ( posedge clk)
a=5;
initial begin
#1000 $finish;
end
endmodule
Race Condition occurs when same register is written in both the blocks. Here you are seeing that one block is updating value of "a" while another also. Now which always block should go first. This is nondeterministic in IEEE standard.
Method 3:
module race2;
bit clk;
reg[3:0] a;
bit b;
always #5 clk=~clk;
always @( posedge clk)
a=1;
always @ ( posedge clk)
b=a;
initial begin
#1000 $finish;
end
endmodule
Race Condition occurs when evaluation and assignment of same variable with the same clk edge.
How to Prevent Race Condition:
- Using Non Blocking Statements
- Using Program Block
- Using Clocking Block
- DUT and TB must be operated on different edges of same clk pulses
Note:
Brief explanation about Program Block and Clocking Block will see on further upcoming Blogs.
Hope this logic's will be useful to everyone !!!
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Nice one. I have a query,
ReplyDeleteMaking assignment operator as non-blocking will not resolve race issue in the code (Method-2) right? I hope we should not assign value to same variable under multiple always block(apart from adding delay). Correct me if i'm wrong.
Hi,
ReplyDeleteThanks for the feedback!!!
Yes you are correct.In method 2 we are assigning same variable in multiple always block with same clk edges. So here we can't predict the order of execution of always block so it leads to race.This is the main reason of in-deterministic nature.Here Race won't be eliminate by non blocking because both are updated in NBA. By adding delay we can eliminate race in method 2.But method 3 we can eliminate by Non blocking assignment.