Applications of Scope Resolution Operator in System Verilog

 Hi Everyone!!!

In this blog We are going to the Applications of  Scope Resolution Operator in System Verilog.

 Scope Resolution operator is denoted as ::  It is used to refer an identifier within the scope of the class. Left side of an scope resolution operator must be class type name, package name, coverage name, typedef name or cover point name and right hand side should be like variable name of any method name(task/function).

Applications:

• Defining Extern Function
• Accessing Static methods
• Using Package parameter accessing without importing in module
• To avoid Name Space Collision

Examples:

1) Defining Extern Function

Extern task and methods can be accessed by using ::

//class

class scope;

  int data;

  extern function void display(); //Here display function is declared as extern

endclass

//Here display function (extern function) is accessed outside of class by using ::

function void scope :: display();

      $display("data = %0d", data);

 endfunction

module tb;

  initial begin

    scope p;

    p = new();

    p.data = 20;

    p.display;

  end

endmodule

OUTPUT

data = 20

2) Accessing Static Methods

Static member of the class is accessed outside of the class by using ::

//class

class scope;

  int a;

  static int b;

   function display(int a,b);

    $display("Values are A=%0d B=%0d",a,b);

  endfunction

endclass

 

module tb;

  initial begin

    scope p;

    p = new();

    p.a=10; // non static member is accessed by class handle(p)

    scope::b = 20;  // static member is accessed by class name with ::

    p.display(p.a,scope::b);

  end

endmodule

OUTPUT:

Values are A=10 B=20

3) Using Package parameter accessing without import in module

Here in package variable "a"is declared. Note that the package has to be included in compilation wherever we use. But not necessarily "imported". This can be achieved by using ::

//package

package scope;

  int a=10;

endpackage

 

module tb;  

  int b;

  initial begin

    b=scope::a;  // without importing variable(a) is accessed here by using ::

    $display(" VALUE %0d",b);

  end

endmodule

OUTPUT:
VALUE 10

4) To avoid name Space Collision

//package

package scope;

  int a=10;

endpackage

 

module tb;  

  int a=15,b,c;

    initial begin

    b=scope::a;  // From package "a" value is assigned to b  (explicitly we mentioned)

    c=a;  // current scope of "a" value is assigned to c

    $display(" VALUE B=%0d C=%0d",b,c);

  end

endmodule

OUPUT:

               VALUE B=10 C=15

Hope this logic's will be useful to everyone !!!

Giving feedback is more precious than writing an article!!! 😊😊😊😊😊

Always welcome both positive and negative feedback's !!!

Feel free to post any queries related SV and UVM  

“Success is getting what you want, happiness is wanting what you get” 

                                            ― W. P. Kinsella