TYPEDEF Class in System Verilog

Hi Everyone !!!

    Today We are going to see the concepts of typedef class in System Verilog.

    A typedef used to provide a forward declaration of the class. In some use case, the class needs to be instantiated/used before the class declaration. For this kind of situation, typedef  is used.

Syntax :

typedef class class_name;

Typedef Examples:

Without typedef

 In the below example. There are two classes class1 and class2. class2 is instantiated class1 and class1 is instantiated class2. Both the classes need the handle of each other. As execution will happen in sequential order. So it leads to compilation error.

//class-1 class class1;   class2 c;    //using class2 handle before declaring it. endclass   //class-2 class class2;   class1 c; endclass    module  tb;   initial begin     class1 c1;     class2 c2;     $display("Inside typedef_class");   end endmodule

OUTPUT:

Error-[SE] Syntax error
Following verilog source has syntax error :
token 'class2' should be a valid type. Please declare it virtual if it
is an Interface.
"test1.sv", 6: token is ';'
class2 c;

With typedef

 When compiler sees typedef class it will know the definition of the class will found on later. The compilation error of the above example can be avoided by using typedef

typedef class class2; //Indication to the compiler class2 might be used before declaration //class-1 class class1;   class2 c;    // compiler knows declaration may come later. endclass   //class-2 class class2;   class1 c; endclass    module tb;   initial begin     class1 c1;     class2 c2;     $display("Inside typedef_class");   end endmodule

OUTPUT:

Inside typedef_class

Hope this logic's will be useful to everyone !!!

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